ON DESIGN OF SELF-TUNING ACTIVE FILTERS

In this paper, we present one approach in design of self-tuning all-pass, band-pass, low-pass and notch filters based on phase control loops with voltage-controlled active components and analyze their stability as well. The main idea is to vary signal delay of the filter and in this way to achieve phase correction. The filter phase characteristics are tuned by varying the transconductance of the operational transconductance amplifier or capacitance of an MOS varicap element, which are the constituents of filters. This approach allows us to implement active filters with capacitance values of order of pF, making the complete filter circuit to be amenable for realization in CMOS technology. The phase control loops are characterized by good controllable delay over the full range of phase and frequency regulation, high stability, and short settling (locking) time. The proposed circuits are suitable for implementation as a basic building RF function block, used in phase and frequency regulation, frequency synthesis, clock generation recovery, filtering, selective amplifying etc

FIFTY YEARS OF MICROPROCESSOR EVOLUTION: FROM SINGLE CPU TO MULTICORE AND MANYCORE SYSTEMS

Nowadays microprocessors are among the most complex electronic systems that man has ever designed. One small silicon chip can contain the complete processor, large memory and logic needed to connect it to the input-output devices. The performance of today's processors implemented on a single chip surpasses the performance of a room-sized supercomputer from just 50 years ago, which cost over $ 10 million [1]. Even the embedded processors found in everyday devices such as mobile phones are far more powerful than computer developers once imagined. The main components of a modern microprocessor are a number of general-purpose cores, a graphics processing unit, a shared cache, memory and input-output interface and a network on a chip to interconnect all these components [2]. The speed of the microprocessor is determined by its clock frequency and cannot exceed a certain limit. Namely, as the frequency increases, the power dissipation increases too, and consequently the amount of heating becomes critical. So, silicon manufacturers decided to design new processor architecture, called multicore processors [3]. With aim to increase performance and efficiency these multiple cores execute multiple instructions simultaneously. In this way, the amount of parallel computing or parallelism is increased [4]. In spite of mentioned advantages, numerous challenges must be addressed carefully when more cores and parallelism are used.This paper presents a review of microprocessor microarchitectures, discussing their generations over the past 50 years. Then, it describes the currently used implementations of the microarchitecture of modern microprocessors, pointing out the specifics of parallel computing in heterogeneous microprocessor systems. To use efficiently the possibility of multi-core technology, software applications must be multithreaded. The program execution must be distributed among the multi-core processors so they can operate simultaneously. To use multi-threading, it is imperative for programmer to understand the basic principles of parallel computing and parallel hardware. Finally, the paper provides details how to implement hardware parallelism in multicore systems

RPLL - RENDEZVOUS PROTOCOL FOR LONG-LIVING SENSOR NODE

Sensor nodes (SNs), as constituents of wireless sensor network (WSN), are battery-powered not rechargeable devices and have limited amount of energy available. Since lifetime of SNs is crucial parameter for energy-efficient WSN design, it is essential to extend their lifetimes as much as possible. Here we propose a rendezvous scheme called Rendezvous Protocol for Long-Living SN, RPLL. This scheme is based on implementation of a duty-cycling technique. For each SN within WSN a unique identification number (ID) is allocated, thanks to which a collision problem is effectively remedied. The RPLL provides on time wake-up of SNs in fully decentralized way and fast detection of new appended SNs. Taking into account the WSN and SN working parameters, such as beacon time, beacon period, number of active SNs, and quartz oscillator instability, by using the proposed method, WSN designer can determine the maximal lifetime of a SN, i.e. to achieve optimal energy consumption

SELF-TUNING LOW-NOISE AMPLIFIER

A low-noise amplifier with a phase control loop is described in this paper. In the proposed circuit, the resonant frequency is auto-tuned to the input signal frequency. In that way, high gain (20 dB), a phase shift of -180o between input and output signals, and good selective characteristics are obtained. The amplifier is robust to parameter variations, ensuring maximal amplification of the input signal regardless of its frequency as long as it is within a specified frequency range (880-950 MHz). Hence, the proposed circuit possesses self-tuning properties. The stability of the phase loop is analyzed by using Lyapunov's control theory

ENERGY HARVESTING TECHNIQUES IN WIRELESS SENSOR NETWORKS

Batteries are the main source of energy for low-power electronics such as micro-electro mechanical systems (MEMS), wireless sensor networks, embedded devices for remote sensing and control, etc. With the limited capacity of finite power sources and the need for supplying energy for the lifetime of a system/device there is a requirement for self-powered devices. Using conventional batteries is not always good design solution because batteries require human intervention to replace them (very often in hard-accessible and harsh-environmental conditions). Therefore, acquiring the electrical power, by using an alternative source of energy that is needed to operate these devices is a major concern. The process of extracting energy from the surrounding environment and converting it into consumable electrical energy is known as energy harvesting or power scavenging. The energy harvesting sources can be used to increase the lifetime and capability of the devices by either replacing or augmenting the battery usage. There are various forms of energy that can be scavenged, like solar, mechanical, thermal, and electromagnetic. Nowadays, there is a big interest in the field of research related to energy harvesting. This paper represents a survey for identifying the sources of energy harvesting and describes the basic operation of principles of the most common energy harvester. As first, we present, in short, the conversion principles of single energy source harvesting systems and point to their benefits and limitations in their usage. After that, hybrid structures of energy harvesters which simultaneously combine scavenged power from different ambient sources (solar, thermoelectric, electromagnetic), with aim to support higher load at the output, are considered

ELEVATOR SYSTEM WITH DUAL POWER SUPPLY

Modern high-rise buildings require use of a growing number of elevators that have become important factors in energy consumption. Most of the existing lifts are powered from the grid. In order to reduce grid energy consumption and increase reliability, an improved elevator system which uses dual power supply is proposed in this paper. This system supplies electronic modules of the elevator with renewable sources whenever there is sufficient sunlight and maintains usual work of the elevator in case of electricity power failure. The corresponding architecture of the proposed elevator system and needed battery capacity for correct operation are given in this paper

Pulse width control loop as a duty cycle corrector

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system’s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital [8]. In this paper, we propose a pulse width control loop referred as MPWCL (modified pulse width control loop) that adopts the same architecture as the conventional PWCL, but with a new pulse generator and new charge pump circuit as a constituent of the duty cycle detector. Thanks to using new building blocks the proposed pulse width control loop can control the duty cycle in a wide range, and what is more important it becomes operative in saturation region too, what provides conditional for fast locking time. For 1.2 µm double-metal double-poly CMOS process with Vdd = 5 V and operating frequency of 133 MHz, results of SPICE simulation show that the duty cycle can be well controlled in the range from 20 % up to 80 % if the loop parameters are properly chosen

Concurrent Generation of Pseudo Random Numbers with LFSR of Fibonacci and Galois Type

We have considered implementation of parallel test pattern generator based on a linear feedback shift register (LFSR) with multiple outputs used as a building block in built-in-self-test (BIST) design within SoC. The proposed design can drive several circuits under test (CUT) simultaneously. The mathematical procedure for concurrent pseudo random number (PRN) generation is described. We have implemented LFSRs that generate two and three PRNs in FPGA and ASIC technology. The design was tested at the operating frequency of 400 MHz. Performance which relate to silicon area, dynamic power consumption and speed of operation were estimated. Synopsis Design Compiler and IHP's 130 nm CMOS ASIC design kit were used for synthesis, routing and mapping of LFSR design. Total silicon area of the LFSR with three parallel outputs and polynomial of degree 32, is 0.012 mm2, and dynamic power consumption is less than 1.3 mW. Obtained results indicate that the area overhead and power consumption are small enough and proportional to the degree of feedback polynomial